VHDL, is it easy, or is it not, is it step forward, or just another complication in achieving the final goal? Do we need another programming language, even if it is meant to put software and hardware together, or we are much better off with pure electronics, soldering the wires, inhaling the fumes? The following report might clarify one’s mind about different approaches in designing digital circuits. A sequential synchronous circuit was designed using VHDL programming method, and then expanded based on the knowledge of the electronic components.
Program code has been debugged and simulated. The resulting waveforms confirmed the expected operation. On the other hand, some of the circuit components have been designed from scratch using digital design techniques. The procedure then has been compared to the programming method Even though, VHDL programming approach may be seen easier and faster, it should be noted that to actually be able not just to program, but to program well, one must have an appropriate ‘vision’ of the problem to be able to implement it in the programming code. And that is not a very transferable skill.
Therefore it is concluded that although majority of designers will benefit from the usage of VHDL programming, some may encounter certain difficulties and ought to use less advanced techniques. Introduction VHDL (Very high speed integrated circuit Hardware Description Language) is a programming language designed for the purposes of description and of the behaviour of digital circuits and systems by function, data flow behaviour and structure. It is used to configure a programmable logic device with a custom logic design. The design of fault free synchronous sequential circuit was carried out.
Two ways of the implementation have been considered: schematic approach and VHDL programming approach. While some may consider schematic approach more logical and hands-on method of designing, an attempt has been made to implement the specifications in the VHDL programming language first. Having debugged the code, separate sequential circuit components have been designed and put together to result in the working schematic implementation. Objectives The designed synchronous sequential circuit will have to take two unsigned 4-bit numbers at the serial input and will output the greater of the two numbers on serial output.
The circuit will include asynchronous Reset input, Clock input, and two synchronous inputs: Start and Data-in. The two synchronous outputs will be: Ready and Data-out. Fig. 1 shows the timing diagram of the expected behaviour of the circuit. The following is a sequence of the circuit events: 1. Upon receiving of the Reset signal (not shown on the diagram), circuit settles in the known “0” state; 2. After one clock event of the Start signal, circuit starts to accept the input data from the Data-in. 3. When all 8 bits are received, the two 4-bit numbers are compared.
4. Once compared, circuit outputs the Ready signal for one clock cycle. 5. After the Ready signal, the largest 4-bit number is outputted serially through the Data-out. Method Before designing any circuit, it is a good idea to picture the major components it is going to be constructed of, and their interconnections. The overall external view of the system to be designed is shown in Fig. 2. Some of the components are combinational devices themselves. Considering the above figure and the timing diagram specified, the following ASM chart has been built.
To further extend the understanding of the circuit functionality, the diagram of the components interconnected together is demonstrated below, and afterwards an explanation will be given as to the sequence of events happening within the circuit. Now that the components diagram is derived, a working sequence of the circuit can be explained. Reset is an asynchronous input clearing the whole circuit independently of the clock and putting gates and flip-flops into known “0” state. Once the Start becomes “1” for 1 clock cycle, the 4-bit counter initiates and starts to count.
Starting from the next clock cycle it generates Enable 1 “1” signal to activate shift register. After 8 clock cycles, counter outputs “0” on the Enable 1 to stop shift register inputting data. At this point all the 8 bits have been propagated along the shift register and are stored in the flip-flops. On the next clock cycle, Enable 2 is activated by the counter to enable comparator Once comparator has taken the two 4-bit numbers, they are compared and when the largest is found, the Ready signal is transmitted for 1 clock cycle. At last, the largest 4-bit number is outputted once, LSB first.