The aim of this report is to give a summary

 

It is defined as the change in output as a percentage of full scale, divided by the percent change in the value of the resistor (Table 1). 5 – Using the counter, display a dynamic ramp, clock signal of counter around 500Hz (Figure 3). Then by changing the MSB resistor, produce a non-monotonic response. The derivation to see if it agrees with theoretical values is presented in the appendix C. 6 – Estimate settling time of the output voltage from full scale to zero 7 – Modify the converter to support two’s complement binary inputs. Experimental Results 2 – The value of the resistor obtained was 15k?.

Rc would then be 7. 5k?. 3 – The values obtained are negative due to the inverting amplifier used. Figure 2 – Voltage level of inputs from 0 to 15. 4 – The set output voltage used was -7,477. The value used for comparisons. 10 % Change in resistorTable 1 – Relationship between change in output and change in resistor values for a full scale operation. 5 – Ramp sasdf dsafasdf adf.

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6 – The settling time was seen to be around 6us. By looking at the negative inverting input of the opamp, a glitch is visible. This shows that the virtual earth does not work at all times. When the input changes from 1111 to 0000 the internal capacitor has to discharge and charge again to achieve zero. 7 – In order to modify the converter to except two’s complement the ladder network was altered as well as the amplifier. A differential summing amplifier was used (figure 6). The ladder network (Figure 1) was connected to this amplifier so that point P was connected to the VA input of the amplifier.

This would invert the MSB to take into account any negative values. Figure 6 – Differential summing amplifier Analogue-to-Digital Conversion Analogue-to-Digital converters are common and therefore are very diverse between them. The choice of which converter to choose normally involves the decision of what factors are more and least important for the job. These factors are speed, accuracy and power consumption. ADCs output and estimate of what the output is and then compares it back with the actual input signal. It will continue to do this until an ideal estimate has been found.

One of the converters used was the Ramp converter (Figure 7). This method uses a digital counter to count upwards starting from zero, which goes through a DAC and compares it to the input signal. When the number is reached by the counter, it stops and our digital number is found. For this to occur accurately, there has to be sufficient time for the number to be converted from digital to analogue and compared with the input signal before continuing counting. The zener-diode is used to pull down any current from going into the nand gate.

The counter shows the nearest equivalent digital value to Vin rounded up due to the fact that the value from the DAC is marginally greater than Vin. Figure 7 – Ramp Converter Experimental Procedure 1 – Using a clock frequency of 5 kHz and a high order bit to provide a counter for the repeating reset command, find the range of dc input voltages corresponding to each digital value and explain any offsets. 2 – Increase clock frequency and find maximum clock frequency at which converter operates correctly. What happens when the frequency exceeds this limit and why ?

Experimental Results 1 – This table is the result from the experiment done. Any voltage in between the lower and upper limit will be equal to the corresponding number. Number Lower Limit Upper limit 0 ….. 7mv 1 7mv 446. 5mv 2 446. 5mv 981mv 3 981mv. Table 2 – Upper and lower limits for each number. 2 – The maximum frequency of the converter is 32. 1 kHz.

The slew rate is the time taken for the output of the amplifier to respond to a change in input, it’s the maximum frequency that the amplifier can operate. The clock period is inversely proportional to the frequency so when the period becomes smaller then the slew rate, it is unable to stop the counter quickly enough so the counter will count one or more values above the correct value until it’s stopped. Successive Approximation Converter The ramp converter is clearly not an ideal converter as the conversion time depends on the amplitude of Vin and can take up to 2n-1 clock cycles for an n-bit converter.

The successive approximation converter is more intelligent and faster, operating at 1 to 10 usec per bit. In this case, the converter performs a binary search for Vin, starting at the midpoint range and asks the comparator which way to go next. The main advantage of the successive approximation converter to the ramp converter is the fact that the ramp converter starts it’s initial count at zero whereas the successive approximator converter starts at a number obtained from a special shift register, Successive Approximation Register (SAR) (Appendix D).

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