Design Instead of performing addition using standard parallel

Design and
implementation of modified radix-4 booth-wallace multiplier in fir filter



Multipliers play a vital role in today’s Digital Signal Processing (DSP),
Microprocessors and in various other applications. Modified Radix-4 Booth
Multipliers are often preferred due to their high performance obtained by
encoding the multiplier bit which reduces the number of partial product
generation to half. Instead of performing addition using standard parallel
adders, Wallace tree uses modified Carry Save Adder (CSA) and Carry Select
Adder (CSLA). By using these high speed adders, product is obtained in less
time. The no. of partial product stages can be further reduced by using
modified CSA and propagation delay is reduced by CSLA. Finally, the
functionality of Modified Radix-4 Booth Multiplier is verified by implementing
it in the design of low pass FIR Filter. The Verilog code is simulated using
INCISIV and synthesized using Cadence Encounter RTL compiler. Simulation
results at 180nm and 45nm technology is provided. The result shows that the
proposed Modified Radix-4 Booth Multiplier is more efficient in terms of power
and delay when compared with conventional booth encoder and Wallace Tree

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Radix-4 Booth Multiplier, Booth encoder, Wallace tree- CSA, CSLA,
signed-unsigned bits.



In digital
computing, multiplication operation is basically considered as an arithmetic
operation as it uses adders and logic gates to generate the output. Shift-Add
algorithm is the basic process used by the multipliers. Multiplication operation
consists of partial product generation and adding these partial product stages
to obtain the final product. Mainly, the speed of operation depends on the
adders and number of partial product stages. Thus the performance of the entire
system depends on the speed of the multiplication process used.

            High speed Booth Multipliers are
used to reduce the power consumption of multiplication operation which in-turn increases
the speed of the entire system. Irregular partial product array is produced
due to the use of extra partial product bits in the LSB of partial product
stages which increases the number of partial product stages. A simple advancement
for generating regular partial product array with reduced number of partial
product stages is used which lowers the complexity and design constraint of
booth multipliers. Modified Booth Sum (S-MB) form is used in multipliers
recoding technique. This uses only one adder and parallel multiplier and due to
the use of redundant signed digit accuracy is lost. In Wallace tree formation
optimized Carry Select Adder is used in the final addition process to eliminate
the redundant logic operation which is data dependent.

            Implementation of signed and
unsigned multiplier uses hybrid adders along with conditional carry adder
and conditional sum adder to reduce delay with increased power consumption. By using
non-redundant radix-4 signed digit encoding multiplier bits are pre-encoded
and stored in ROM which is area and power efficient. Approximate computing
is useful when accuracy is not considered as a major parameter. Approximate Wallace
tree formation is used to generate the regular partial product array. Error may
appear due to the use of approximation technique which produces only the
approximate product and not the actual product. Instead of using fast adders in
the final addition stage, redundant binary adders are used which reduces delay.
Approximate Wallace tree multipliers are used for error-tolerant applications
due to the power and area efficiency. To reduce critical path, carry-in
prediction is used which increases the power consumption.

            In Wallace tree formation stage,
Carry Save Adder plays a vital role in reducing the partial product generation
stages. Using multiplexer based full adders in CSA structure power and delay is
reduced. In Wallace tree formation stages compressors or counters are mainly used
to add the partial products . Approximate compressors are proposed in and
used in Dadda Multiplier. Approximate adders are designed in which does not
take into account of the carry propagation between partial products. By applying
hybrid approximation technique power savings for similar error values is
obtained. Approximate adders are used in the design of radix-8 booth multiplier
which uses two bit adder for generating the odd multiples of the multiplicand.     


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