Design andimplementation of modified radix-4 booth-wallace multiplier in fir filter Abstract:Multipliers play a vital role in today’s Digital Signal Processing (DSP),Microprocessors and in various other applications.
Modified Radix-4 BoothMultipliers are often preferred due to their high performance obtained byencoding the multiplier bit which reduces the number of partial productgeneration to half. Instead of performing addition using standard paralleladders, Wallace tree uses modified Carry Save Adder (CSA) and Carry SelectAdder (CSLA). By using these high speed adders, product is obtained in lesstime. The no. of partial product stages can be further reduced by usingmodified CSA and propagation delay is reduced by CSLA. Finally, thefunctionality of Modified Radix-4 Booth Multiplier is verified by implementingit in the design of low pass FIR Filter. The Verilog code is simulated usingINCISIV and synthesized using Cadence Encounter RTL compiler.
Simulationresults at 180nm and 45nm technology is provided. The result shows that theproposed Modified Radix-4 Booth Multiplier is more efficient in terms of powerand delay when compared with conventional booth encoder and Wallace TreeMultiplier. IndexTerms—ModifiedRadix-4 Booth Multiplier, Booth encoder, Wallace tree- CSA, CSLA,signed-unsigned bits. 1 INTRODUCTIONIn digitalcomputing, multiplication operation is basically considered as an arithmeticoperation as it uses adders and logic gates to generate the output. Shift-Addalgorithm is the basic process used by the multipliers. Multiplication operationconsists of partial product generation and adding these partial product stagesto obtain the final product.
Mainly, the speed of operation depends on theadders and number of partial product stages. Thus the performance of the entiresystem depends on the speed of the multiplication process used. High speed Booth Multipliers areused to reduce the power consumption of multiplication operation which in-turn increasesthe speed of the entire system. Irregular partial product array is produceddue to the use of extra partial product bits in the LSB of partial productstages which increases the number of partial product stages. A simple advancementfor generating regular partial product array with reduced number of partialproduct stages is used which lowers the complexity and design constraint ofbooth multipliers. Modified Booth Sum (S-MB) form is used in multipliersrecoding technique. This uses only one adder and parallel multiplier and due tothe use of redundant signed digit accuracy is lost.
In Wallace tree formationoptimized Carry Select Adder is used in the final addition process to eliminatethe redundant logic operation which is data dependent. Implementation of signed andunsigned multiplier uses hybrid adders along with conditional carry adderand conditional sum adder to reduce delay with increased power consumption. By usingnon-redundant radix-4 signed digit encoding multiplier bits are pre-encodedand stored in ROM which is area and power efficient.
Approximate computing is useful when accuracy is not considered as a major parameter. Approximate Wallacetree formation is used to generate the regular partial product array. Error mayappear due to the use of approximation technique which produces only theapproximate product and not the actual product.
Instead of using fast adders inthe final addition stage, redundant binary adders are used which reduces delay.Approximate Wallace tree multipliers are used for error-tolerant applicationsdue to the power and area efficiency. To reduce critical path, carry-inprediction is used which increases the power consumption. In Wallace tree formation stage,Carry Save Adder plays a vital role in reducing the partial product generationstages.
Using multiplexer based full adders in CSA structure power and delay isreduced. In Wallace tree formation stages compressors or counters are mainly usedto add the partial products . Approximate compressors are proposed in andused in Dadda Multiplier. Approximate adders are designed in which does nottake into account of the carry propagation between partial products. By applyinghybrid approximation technique power savings for similar error values isobtained.
Approximate adders are used in the design of radix-8 booth multiplierwhich uses two bit adder for generating the odd multiples of the multiplicand.